As technology continues to advance, processor clock frequency increases with edge rates reduce to sub-nano second range. The performance is no longer determined only by the device technology but also influenced significantly by interconnects. As timing budget reduces because of higher speed, it increases the timing uncertainty of the digital signal. This causes a design that works well in the laboratory to become unreliable when integrated onto the printed circuit boards (PCBs). Hence, the issue of SI can no longer be neglected and must be characterized and modelled with good accuracy. Furthermore, faster operating speed leads to wider frequency bandwidth, the transmission line and parasitic effects of interconnects have to be accounted for. The layout of board is equally crucial and any minor flaw in high-speed digital board layout can easily cause the system to fail the EMI regulatory limits.
In view of the importance of SI and EMI radiation in high-speed digital circuit, the proposed project aims to achieve the following objectives:
a) Board Level Signal Integrity
b) Board Level Radiated EMI Analysis 

Signal Integrity